Researchers at imec and Ghent University demonstrated growing 120 alternating layers of silicon (Si) and silicon-germanium (SiGe) on full 300mm production wafers using precision epitaxial deposition. Each stack comprises ~65nm silicon and 10nm Si0.8Ge0.2 layers repeated 120 times, totaling ~1.2μm thickness while remaining fully strained without threading dislocations in the wafer interior. This overcomes thermal expansion mismatches and defect propagation that previously limited 3D DRAM to ~32 layers, enabling exponentially higher memory density for AI accelerators alongside Gate-All-Around (GAAFET) transistors and quantum-optimized logic. The process uses reduced-pressure CVD with silane for silicon and dichlorosilane/germane for SiGe at 675°C, maintaining sharp interfaces and uniform thickness despite reactor quartz tube buildup challenges. Coming amid TSMC’s N2 2nm HVM ramp and HBM4 doubling bandwidth needs, this vertically scales memory where planar limits hit physics, positioning 3D-stacked DRAM as essential for exascale AI clusters by 2027-2028.
Source: NotebookCheck
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